Semiconductor Engineering

Customizing A LLM Model For VHDL Design of High-Performance MPUs (IBM)

A new technical paper titled “Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors” was published by researchers at IBM. “The use of Large Language Models (LLMs) in ...
GitHub

[GHDL / Modelsim] Simulation fails if path contains whitespaces

If the sources are in a holder with white spaces, a simulation using Modelsim or GHDL will fail. I assume this is because the paths are not passed over with quotation marks. Here the log for ghdl 2024 ...
Hackaday

Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

Soft cores for FPGAs come in many different flavors, covering a wide range of applications. The Bit-Serial CPU (bcpu) soft core presented by [Richard James Howe] is interesting for taking up just ...
IEEE

Simulink/Modelsim Simulabel VHDL PID Core for Industrial SoPC Multiaxis Controllers

Abstract: This paper presents a PID controller core described in VHDL suitable to be introduced into a system-on-programmable chip design. The flexibility of the system-on-a-programmable-chips (SoPCs) ...
Hackaday

Using VHDL To Generate Discrete Logic PCB Designs

VHDL and Verilog are hardware description languages, used to describe and define logic circuits. They’re typically used to design ASICs and to program FPGAs, essentially using software to define ...
archive

Introduction to Simulation of VHDL Designs Using ModelSim

Ask the publishers to restore access to 500,000+ books. An icon used to represent a menu that can be toggled by interacting with this icon. A line drawing of the Internet Archive headquarters building ...
GitHub

My projects in VHDL language for FPGA in Modelsim software

This VHDL code represents a simple pseudorandom number generator (PRNG) designed with a Linear Feedback Shift Register (LFSR). The LFSR PRNG generates a sequence of pseudo-random bits based on the ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Electronic Specifier

VHDL/Verilog Converters upgraded for Verilog 2005

The Verilog2VHDL tool now supports the following Verilog 2005 constructs: multi-dimensional arrays, signed regs and nets that convert to VHDL numeric_std.signed data types, Verilog 2005 event control ...